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// VLSI Engineer

Sarun K

VLSI Design & Verification Engineer

Designing reliable digital systems through RTL Design and Functional Verification.

Electronics and Instrumentation Engineering Graduate passionate about Digital Design, RTL Development, Functional Verification, and Semiconductor Technology.

Sarun K — VLSI Engineer

01 / Profile

About Me

Sarun K

I am an Electronics and Instrumentation Engineering graduate from Puducherry Technological University with a strong passion for Digital Design, RTL Development, and Functional Verification.

Currently pursuing Advanced VLSI Design and Verification training, I have hands-on experience in Verilog, SystemVerilog, UVM, and protocol verification. My interests lie in designing and verifying reliable digital systems that power modern semiconductor products.

I chose VLSI because of my passion for electronics and chip design. What excites me most about VLSI is its vast scope and its role at the core of modern technology — being part of the process that powers everyday electronic devices motivates me to build a career as a Design and Verification Engineer.

RTL Design
Verification
Semiconductor Tech
Problem Solving

02 / Journey

Education

B.Tech, Electronics & Instrumentation Engineering

Puducherry Technological University

Graduated: 2025 · CGPA: 6.86

Higher Secondary Education

I K Kumaran Govt Higher Secondary School

Percentage: 83.33%

Secondary School Education

I K Kumaran Govt Higher Secondary School

Percentage: 94%

03 / Expertise

Skills

HDL & Verification Languages

Verilog90%
SystemVerilog88%
UVM85%

RTL Design

FSM Design88%
Counter Design90%
RTL Coding87%
Digital Logic Design90%

Functional Verification

UVM Testbench85%
Functional Coverage82%
Assertions80%
Scoreboard85%
Constrained Random83%
Protocol Verification85%

Protocols

AXI385%
APB88%
SPI88%

Tools

Synopsys VCS85%
Verdi82%
Vivado85%
Xilinx ISE80%
Linux78%

Programming

C82%

04 / Work

Projects

05 / Certification

Training

Advanced VLSI Design and Verification

Comprehensive industry-aligned training program

VerilogSystemVerilogUVMRTL DesignFunctional VerificationAssertionsCoverage Driven VerificationProtocol Verification

06 / Hiring

Open to Opportunities

Current Focus

  • RTL Design
  • Functional Verification
  • UVM Verification
  • Protocol Verification

Looking For

  • VLSI Design Engineer
  • Design Verification Engineer
  • RTL Design Engineer
  • FPGA Engineer
  • Graduate Engineer Trainee (VLSI)

Preferred Locations

BangaloreHyderabadChennaiPuneKochiThiruvananthapuram

Open to Relocate Across India

Availability

Immediate Joiner

Ready to contribute from day one

Dream Companies

NVIDIA

Qualcomm

AMD

Samsung Semiconductor

MediaTek

Cadence

GitHub — Coming Soon

Future Repositories

AXI VerificationUVM ProjectsRTL Design ProjectsVerification IPs

07 / Credential

Certification

Advanced VLSI Design & Verification

Maven SiliconJune 2025 – February 2026Course Completion Certificate

Successfully completed an industry-oriented Advanced VLSI Design & Verification program covering RTL Design, Verilog, SystemVerilog, UVM, Digital Design, ASIC Design Flow, Functional Verification, and industry-standard EDA tools through hands-on laboratory sessions and engineering projects.

07 / Connect

Get in Touch

Sarun K

Sarun K

Open to Relocate

Send a Message